调测UART串口VerilogHDL通信fpga逻辑工程源码+自定义协议说明.zip

[{"title":"（108个子文件2.53MB）调测UART串口VerilogHDL通信fpga逻辑工程源码+自定义协议说明.zip","children":[{"title":"调测UART串口下位机与上位机通信协议说明.docx <span style='color:#111;'>14.27KB</span>","children":null,"spread":false},{"title":"usbkey_ctrl.v <span style='color:#111;'>35.92KB</span>","children":null,"spread":false},{"title":"rs232rx.v <span style='color:#111;'>6.22KB</span>","children":null,"spread":false},{"title":"rx_frame.v <span style='color:#111;'>3.22KB</span>","children":null,"spread":false},{"title":"clock_gen_select.v <span style='color:#111;'>3.26KB</span>","children":null,"spread":false},{"title":"......","children":null,"spread":false},{"title":" <span style='color:steelblue;'>文件过多，未全部展示</span>","children":null,"spread":false}],"spread":true}]