EP4CE22F17C8CYCLONEIVEFPGA开发板ALTIUM设计原理图+PCB+封装文件+FPGA源码.zip

[{"title":"（35个子文件58.75MB）EP4CE22F17C8CYCLONEIVEFPGA开发板ALTIUM设计原理图+PCB+封装文件+FPGA源码.zip","children":[{"title":"测试代码","children":[{"title":"KEY1_KEY2_edge.zip <span style='color:#111;'>4.53MB</span>","children":null,"spread":false},{"title":"W5200_LED.zip <span style='color:#111;'>2.85MB</span>","children":null,"spread":false},{"title":"LED_EPCS16.zip <span style='color:#111;'>2.61MB</span>","children":null,"spread":false},{"title":"LED_W5200.zip <span style='color:#111;'>2.34MB</span>","children":null,"spread":false},{"title":"SDRAM2.zip <span style='color:#111;'>7.34MB</span>","children":null,"spread":false},{"title":"UART.zip <span style='color:#111;'>2.24MB</span>","children":null,"spread":false},{"title":"TIME.zip <span style='color:#111;'>2.17MB</span>","children":null,"spread":false},{"title":"SPI_W25Q64.zip <span style='color:#111;'>2.04MB</span>","children":null,"spread":false},{"title":"hello_world.zip <span style='color:#111;'>2.06MB</span>","children":null,"spread":false},{"title":"KEY2_edge.zip <span style='color:#111;'>4.65MB</span>","children":null,"spread":false},{"title":"PWM_CUSTON_IP.zip <span style='color:#111;'>2.40MB</span>","children":null,"spread":false},{"title":"SPI_W25Q64_simulation.zip <span style='color:#111;'>2.09MB</span>","children":null,"spread":false},{"title":"SDRAM1.zip <span style='color:#111;'>20.67MB</span>","children":null,"spread":false},{"title":"SD_card.zip <span style='color:#111;'>2.45MB</span>","children":null,"spread":false}],"spread":false},{"title":"EP4CE22F17C8FPGA开发板原理图PCB","children":[{"title":"EP4CE22F17C8FPGA开发板.PcbLib <span style='color:#111;'>204.50KB</span>","children":null,"spread":false},{"title":"FPGA_Power.SchDoc <span style='color:#111;'>367.00KB</span>","children":null,"spread":false},{"title":"EP4CE22F17C8FPGA开发板.PcbDoc <span style='color:#111;'>2.14MB</span>","children":null,"spread":false},{"title":"AUDIO_WM8731.SchDocPreview <span style='color:#111;'>65.15KB</span>","children":null,"spread":false},{"title":"FPGA_BANK.SchDocPreview <span style='color:#111;'>95.89KB</span>","children":null,"spread":false},{"title":"INTERFACE.SchDocPreview <span style='color:#111;'>98.39KB</span>","children":null,"spread":false},{"title":"FPGA_BANK.SchDoc <span style='color:#111;'>886.50KB</span>","children":null,"spread":false},{"title":"INTERFACE.SchDoc <span style='color:#111;'>160.00KB</span>","children":null,"spread":false},{"title":"FPGA_Power.SchDocPreview <span style='color:#111;'>42.35KB</span>","children":null,"spread":false},{"title":"FPGA_JTAG.SchDoc <span style='color:#111;'>161.50KB</span>","children":null,"spread":false},{"title":"EP4CE22F17C8FPGA开发板.PcbDocPreview <span style='color:#111;'>212.80KB</span>","children":null,"spread":false},{"title":"ETHERNET_W5200.SchDoc <span style='color:#111;'>154.00KB</span>","children":null,"spread":false},{"title":"POWER.SchDocPreview <span style='color:#111;'>28.91KB</span>","children":null,"spread":false},{"title":"SDRAM.SchDocPreview <span style='color:#111;'>56.49KB</span>","children":null,"spread":false},{"title":"EP4CE22F17C8FPGA开发板.PrjPCB <span style='color:#111;'>32.99KB</span>","children":null,"spread":false},{"title":"EP4CE22F17C8FPGA开发板.PrjPCBStructure <span style='color:#111;'>54B</span>","children":null,"spread":false},{"title":"AUDIO_WM8731.SchDoc <span style='color:#111;'>112.50KB</span>","children":null,"spread":false},{"title":"POWER.SchDoc <span style='color:#111;'>35.50KB</span>","children":null,"spread":false},{"title":"FPGA_JTAG.SchDocPreview <span style='color:#111;'>52.48KB</span>","children":null,"spread":false},{"title":"ETHERNET_W5200.SchDocPreview <span style='color:#111;'>59.28KB</span>","children":null,"spread":false},{"title":"SDRAM.SchDoc <span style='color:#111;'>128.50KB</span>","children":null,"spread":false}],"spread":false}],"spread":true}]