CycloneIVEP4CE6F17C8FPGA开放板硬件设计文件AD版原理图+PCB(4层板).zip

[{"title":"（11个子文件3.18MB）CycloneIVEP4CE6F17C8FPGA开放板硬件设计文件AD版原理图+PCB(4层板).zip","children":[{"title":"CycloneIVEP4CE6F17C8FPGA开放板硬件设计文件AD版原理图+PCB(4层板)","children":[{"title":"2_FPGA.SchDoc <span style='color:#111;'>410.50KB</span>","children":null,"spread":false},{"title":"EP4CE6F17C8FPGA开发板.PcbDoc <span style='color:#111;'>2.26MB</span>","children":null,"spread":false},{"title":"6_DIG.SchDoc <span style='color:#111;'>247.00KB</span>","children":null,"spread":false},{"title":"4_FPGA.SchDoc <span style='color:#111;'>867.00KB</span>","children":null,"spread":false},{"title":"EP4CE6F17C8FPGA开发板原理图用户手册.pdf <span style='color:#111;'>1.94MB</span>","children":null,"spread":false},{"title":"7_VGA.SchDoc <span style='color:#111;'>225.00KB</span>","children":null,"spread":false},{"title":"3_FPGA.SchDoc <span style='color:#111;'>411.00KB</span>","children":null,"spread":false},{"title":"EP4CE6F17C8FPGA开发板原理图.pdf <span style='color:#111;'>131.31KB</span>","children":null,"spread":false},{"title":"5_SDRAM.SchDoc <span style='color:#111;'>72.50KB</span>","children":null,"spread":false},{"title":"EP4CE6F17C8FPGA开发板.PrjPCB <span style='color:#111;'>42.43KB</span>","children":null,"spread":false},{"title":"1_POWER.SchDoc <span style='color:#111;'>157.00KB</span>","children":null,"spread":false}],"spread":false}],"spread":true}]