七段数码管时钟显示的硬件实现verilog

[{"title":"（568个子文件8.62MB）七段数码管时钟显示的硬件实现verilog","children":[{"title":"cpu_0_rf_ram_a.mif <span style='color:#111;'>600B</span>","children":null,"spread":false},{"title":"SEG7_Timer.asm.rpt <span style='color:#111;'>6.99KB</span>","children":null,"spread":false},{"title":"SRAM_16Bit_512K.v <span style='color:#111;'>809B</span>","children":null,"spread":false},{"title":"SEG7_Timer.map.summary <span style='color:#111;'>478B</span>","children":null,"spread":false},{"title":"cpu_0.v <span style='color:#111;'>382.20KB</span>","children":null,"spread":false},{"title":"......","children":null,"spread":false},{"title":" <span style='color:steelblue;'>文件过多，未全部展示</span>","children":null,"spread":false}],"spread":true}]